Due to the dynamics of the information era and its demanding nature, the bar for information technology (IT) companies to produce highly reliable equipment is constantly being raised. The reliability of IT equipment may be a significant factor to designing highly fault tolerant datacenters. As such, processor vendors may need to account for imperfections in the manufacturing process through the use of appropriate stress tests.
Such tests may ensure proper coverage to validate safe operation in the face of issues such as process variation and circuit aging prior to shipment. This problem may be exacerbated as the process technology continues to shrink making CMOS based designs less reliable. Caches are generally one of the most susceptible structures due to their sensitivity to imbalances in transistor behavior present in a given static random access memory (SRAM) cell.